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By Norman G. Einspruch

Includes contributions from a dozen execs from the inner most quarter and academia. Discusses numerous equipment physics subject matters of specific curiosity to and collage researchers in electric engineering, computing device technology, and digital fabrics. Emphasizes actual description, mode

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33. M. C. Jeng, J. Chung, A. Wu, J. Moon, T. Y. Chan, G. May, P. K. Ko, and C. Hu, Performance and reliability of deep-submicron M O S F E T s . Tech. —Int. , p. 710 (1987). 34. S. Y. Chou and D. A. Antoniadias, Relationship between measured and intrinsic transcon­ ductance of FETs. IEEE Trans. Electron Devices ED-34, 448 (1987). 35. T. Toyabe et al, A numerical model of avalanche breakdown in MOSFETs. IEEE Trans. Electron Devices ED-25, 825-834 (1978). 36. S. Selberherr, A. Schutz, and H. W. Potzl, M I N I M O S — A two-dimensional MOS transistor analyzer.

From Huang et al. ) 1 3 13 2 - 2 2 2 13 - 2 2 In the submicron range, standard L D D devices are unlikely to be adequate for 5-V operation. 8-(xm gate-length transistors with adequate lifetimes at 5 V have been achieved using a variety of modified L D D structures, including buried [16], double implanted [17], and conductive spacer [18] schemes. D. Depletion-Mode n-Channel Transistors So far in this section, we have considered only enhancement-mode nchannel devices, that is, those which do not conduct with zero gate-to-source Alan G.

In general, p~ channel devices continue to be fabricated using ndoped polysilicon gates. The most c o m m o n method used to set a suitable /7-channel threshold voltage is p-type (boron) ion implantation. -type layer at the channel surface [23]. -channel doping profile is shown in Fig. 9a, while Fig. 9b shows the vertical 56 Alan G. Lewis and John Y. Chen log of net d o p i n g concentration A shallow p-type i m p l a n t depth potential t potential m i n i m u m at buried channel depth Fig. 9.

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